1. Field
The present disclosure generally relates to circuits. More specifically, the present disclosure relates to an integrated circuit that assesses an on-chip input/output (I/O) circuit based on an asymmetry of an eye pattern associated with the I/O circuit.
2. Related Art
The performance of high-performance input/output (I/O) circuits, such as high-speed serial links, is often dependent on the accuracy of the impedance matching and impedance balancing between the transmitter circuit, the receiver circuit and the communication channel that couples these components. For example, the impedance matching may include: the resistances of the termination resistors, trace resistances and connector contact resistances.
During manufacturing, deviations from the nominal values for these resistances can occur. For example, the traces and/or the connectors may inadvertently include resistance differences on differential signal lines, such as those associated with open, partially open, shorted or partially shorted components.
If any of the components in a high-performance I/O circuit deviates from the design or nominal values, the transfer function and, thus, the signal properties may be significantly changed. In turn, these changes may significantly degrade the margin of the I/O circuit, with a commensurate impact on performance, stability and reliability.
As a consequence, qualification testing is typically performed during or immediately after manufacturing to identify any deviations in the specified values of the components in high-speed I/O circuits. However, as circuits become increasingly complicated, testing is becoming more time consuming and expensive. Furthermore, proper testing of a high-performance I/O circuit is often not possible until this circuit is integrated into a larger system, which may occur long after the circuit is manufactured.
Hence, what is needed are an I/O circuit and an associated testing technique that do not suffer from the above-described problems.